The present invention generally relates to physical random number generators (i.e., a device that generates a bit or bits representative of a number by operating one or more components of the device in an undeterminable manner). The present invention specifically relates to an operational efficiency of a physical random number generator that facilitates an incorporation of the physical random number generator within various types of electronic devices.
FIG. 1 illustrates one possible way to provoke a metastable state of a bi-stable latch via one or more inputs to the bi-stable latch. When a voltage level of each input of the bi-stable latch equals or exceeds a high logic voltage level VHL, each output of the bi-stable latch can be pre-determined with a high degree of certainty (i.e., a stable state). Similarly, when a voltage level of each input of the bi-stable latch equals or is lower than a low logic voltage level VLL, each output of the bi-stable latch can again be pre-determined with a high degree of certainty. Conversely, when a voltage level of any input of the bi-stable latch is between the high logic voltage level VHL and the low logic voltage level VLL (i.e., an indeterminate range), each output of the bi-stable latch can""t be pre-determined with any degree of certainty (i.e., the metastable state).
The present invention provokes a metastable state of a bi-stable latch as a basis of a physical random number generator. Various aspects of the present invention are novel, non-obvious, and provide various advantages. While the actual nature of the present invention covered herein can only be determined with reference to the claims appended hereto, certain features, which are characteristic of the embodiments disclosed herein, are described briefly as follows.
One form of the present invention is a physical random number generator comprising an oscillator and a bi-stable latch, and a switch. When the bi-stable latch is deactivated, the oscillator is activated to provide one or more voltage oscillating signals, each voltage oscillating signal having an unpredictable logic voltage level. When the oscillator is deactivated, the bi-stable latch is activated to receive the voltage oscillation signal(s) and to latch a random number bit as a function of the unpredictable logic voltage level of each voltage oscillating signal at a time of reception of the voltage oscillating signal(s) by the bi-stable latch.
The foregoing form as well as other forms, features and advantages of the present invention will become further apparent from the following detailed description of the presently preferred embodiments, read in conjunction with the accompanying drawings. The detailed description and drawings are merely illustrative of the present invention rather than limiting, the scope of the present invention being defined by the appended claims and equivalents thereof.